Job Title: Senior Digital Logic Design Engineer
Responsibilities:
- Develop micro-architecture and RTL design for digital components for DDR memory buffer products.
- Setup and analyze lint, synthesis, timing, and DFT reports to ensure optimal performance and design integrity.
- Support design verification, physical design, DFT, and post-silicon validation activities.
- Collaborate effectively with cross-functional teams and demonstrate a high level of self-motivation and attention to detail.
- Contribute to project milestones and ensure quality delivery within deadlines.
Requirements and Qualifications:
- MS/M-Tech in Electronics/VLSI or B.E/B-Tech in Electronics Engineering with relevant experience in digital logic design.
- A minimum of 3 years of experience in Digital Logic Design, including work with multiple clock domains and familiarity with synthesis flows.
- Solid understanding of high-speed chip-to-chip interfaces such as memory PHY, SerDes, and Chiplet/UCIe PHY is a strong plus.
- Expertise in RTL design, particularly using Verilog.
- Experience with scripting and automation tools to streamline design and verification processes.
- Strong analytical and troubleshooting skills with the ability to work in a fast-paced, collaborative environment.
